1. Field of the Invention
The present invention relates generally to the field of computer systems, and specifically, to a method and apparatus for minimizing asynchronous transmit FIFO under-run and receive FIFO over-run conditions.
2. Background Information
A general purpose computer system typically includes a processor, memory, and one or more peripheral devices coupled together by one or more buses. Recently, serial peripheral buses (e.g., a universal serial bus "USB", a 1394 serial bus, IEEE 1394-1995 High Performance Serial Bus IEEE, 1995, etc.) have become increasingly popular in computer systems mainly because they offer a low cost, high performance alternative to other bus architectures. A serial bus architecture typically includes transmit and receive first-in/first-out devices ("FIFOs"), an interface module which interfaces between the computer system bus and the FIFOs, and a serial interface module that operates as an interface between the serial bus (and one or more peripheral devices on the serial bus) and the FIFOs. These serial buses transmit and receive asynchronous data as well as isochronous data depending on the peripheral device coupled to the serial bus. Asynchronous transmission places emphasis on guaranteed delivery of data over guaranteed timing whereas isochronous transmission places emphasis on guaranteed timing of data over delivery of data.
For data transmission, the host processor creates a context program in memory, the context program including data and commands. The commands direct how the data is to be assembled for transmission, the destination of the data packets, etc. The interface module retrieves the commands and data packets from memory and places them into the transmit FIFO. However, before data can be read from memory, the interface module must request access to gain control of the system bus. The time that it takes to gain control (referred to as "system bus latency") of the system bus is non-deterministic and depends on several factors including the bus speed, the number of devices requesting access to gain control of the bus, and the like.
As soon as data is placed in the transmit FIFO, transmit FIFO control circuitry requests to transmit the data on the serial bus. Similarly, the time that it takes for a serial bus grant (referred to as "serial bus latency") is non-deterministic and depends on a number of factors including the serial bus speed, the number of serial peripheral devices on the serial bus, and the amount of isochronous traffic. Once access is granted, the data is transmitted on the serial bus. If the data packet size to be transmitted is greater than the transmit FIFO size, portions (or the balance) of the data packet must be retrieved from memory as the data is drained from the transmit FIFO onto the serial bus. However, if the system bus latency for retrieving the balance of the data packet is greater than the time that it takes to drain the transmit FIFO, an under-run condition will occur. The chances of an under-run condition occurring rapidly increases in a computer system having a heavy traffic on the system bus. An under-run condition is undesirable because it wastes serial bus bandwidth, thus slowing the system down.
Accordingly, there is a need in the technology for a method and apparatus to minimize/prevent an asynchronous transmit FIFO under-run condition due to system latencies.
Data that is received from a peripheral device on the serial bus in a receive FIFO is placed in memory for processing by the processor. In this case, if data is not placed in memory fast enough, a data over-run condition may occur (i.e., when data is received by a full FIFO to cause data already in the FIFO to be overwritten). The depth of the receive FIFO is one factor in determining the system bus latency that the FIFO can handle without an over-run condition occurring. The issue of system bus latency is exacerbated by the fact that the interface module may need to fetch commands from memory prior to being able to write data from the receive FIFO into memory. That is, a typical asynchronous packet may require a command fetch, data storage, and status write-back, all to different locations in memory. If many small asynchronous packets are received in the receive FIFO, the system bus latency required to fetch commands from and complete the status write-back to memory may greatly exceed the time required to drain the data from the receive FIFO.
Accordingly, there is a further need in the technology for a method and apparatus to eliminate over-run conditions in a receive FIFO.